Semiconductor device

ABSTRACT

A semiconductor device including a nonvolatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that a predetermined amount of charge is held at the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

TECHNICAL FIELD

The invention disclosed herein relates to a semiconductor device including a semiconductor element and a manufacturing method of the semiconductor device.

BACKGROUND ART

Memory devices including semiconductor elements are broadly classified into two categories: volatile memory devices that lose stored data when not powered, and nonvolatile memory devices that hold stored data even when not powered.

A typical example of volatile memory devices is a dynamic random access memory (DRAM). A DRAM stores data in such a manner that a transistor included in a memory element is selected and electric charge is stored in a capacitor.

When data is read from a DRAM, electric charge in a capacitor is lost according to the above-described principle; thus, another writing operation is necessary every time data is read out. Moreover, a transistor included in a memory element has leakage current (off-state current) between a source and a drain in an off state or the like and electric charge flows into or out of the transistor even if the transistor is not selected, which makes a data holding period short. For that reason, writing operation (refresh operation) is necessary at predetermined intervals, and it is difficult to sufficiently reduce power consumption. Furthermore, since stored data is lost when power supply stops, another memory device utilizing a magnetic material or an optical material is needed in order to hold the data for a long time.

Another example of volatile memory devices is a static random access memory (SRAM). An SRAM holds stored data by using a circuit such as a flip-flop and thus does not need refresh operation, which is an advantage over a DRAM. However, cost per storage capacity is high because a circuit such as a flip-flop is used. Moreover, as in a DRAM, stored data in an SRAM is lost when power supply stops.

A typical example of nonvolatile memory devices is a flash memory. A flash memory includes a floating gate between a gate electrode and a channel formation region in a transistor and stores data by holding charge in the floating gate. Therefore, a flash memory has advantages in that the data holding period is extremely long (semi-permanent) and refresh operation which is necessary to volatile memory devices is not needed (e.g., see Patent Document 1).

However, in a flash memory, there is a problem in that a memory element becomes unable to function after a predetermined number of writing operations because a gate insulating layer included in the memory element deteriorates due to tunneling current generated in writing operations. In order to reduce effects of this problem, a method in which the number of writing operations is equalized among memory elements can be employed, for example, but a complex peripheral circuit is needed to realize this method. Moreover, even when such a method is employed, the fundamental problem of lifetime cannot be resolved. In other words, a flash memory is not suitable for applications in which data is frequently rewritten.

In addition, high voltage is necessary in order to inject charge into the floating gate or removing the charge, and a circuit therefor is required. Further, it takes a relatively long time to inject or remove electric charge, and it is not easy to increase the speed of writing or erasing data.

REFERENCE

-   [Patent Document 1] Japanese Published Patent Application No.     S57-105889

DISCLOSURE OF INVENTION

In view of the foregoing problems, an object of one embodiment of the disclosed invention is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles.

In one embodiment of the disclosed invention, a semiconductor device is formed using a material capable of sufficiently reducing the off-state current of a transistor, such as an oxide semiconductor material that is a widegap semiconductor. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor allows data to be held for a long time.

Further, one embodiment of the disclosed invention provides a semiconductor device including a nonvolatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where one of a source electrode and a drain electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that a predetermined amount of charge is held at the node. Further, when a p-channel type transistor is used as the reading transistor, a reading potential is a positive potential.

More specifically, the following structures can be employed, for example.

An embodiment of the present invention is a semiconductor device including a memory cell including a first transistor, a second transistor, and a capacitor. The first transistor is a p-channel type transistor and includes a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region. The second transistor includes a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region which includes a semiconductor material different from that of the first channel formation region. The first gate electrode, the second drain electrode, and one electrode of the capacitor are electrically connected to each other and form a node where electric charge is held.

Another embodiment of the present invention is a semiconductor device including first to fifth wirings and a memory cell connected between the first wiring and the second wiring. The memory cell includes: a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region which includes a semiconductor material different from that of the first channel formation region; and a capacitor. The first transistor is a p-channel type transistor. The first gate electrode, the second drain electrode, and one electrode of the capacitor are electrically connected to each other and form a node where electric charge is held. The first wiring and the first source electrode are electrically connected to each other. The second wiring and the first drain electrode are electrically connected to each other. The third wiring and the second source electrode are electrically connected to each other. The fourth wiring and the second gate electrode are electrically connected to each other. The fifth wiring and the other electrode of the capacitor are electrically connected to each other.

In each of the above semiconductor devices, the second channel formation region preferably includes an oxide semiconductor.

In each of the above semiconductor devices, the second transistor is preferably provided so as to overlap with at least part of the first transistor.

In each of the above semiconductor devices, the first channel formation region may include silicon.

In each of the above semiconductor devices, the second transistor may be an n-channel type transistor.

Note that although, in the above embodiments, the transistor may be formed using an oxide semiconductor, the disclosed invention is not limited thereto. A material capable of realizing off-state current characteristics comparable to those of an oxide semiconductor, for example, a widegap material (more specifically, a semiconductor material having an energy gap Eg of more than 3 eV, for example), such as silicon carbide, or the like may be employed.

Note that the term such as “over” or “below” in this specification and the like does not necessarily mean that a component is placed “directly on” or “directly under” another component. For example, the expression “a gate electrode over a gate insulating layer” does not exclude the case where a component is placed between the gate insulating layer and the gate electrode.

In addition, the term such as “electrode” or “wiring” in this specification and the like does not limit a function of a component. For example, an “electrode” can be used as part of a “wiring”, and the “wiring” can be used as part of the “electrode”. Furthermore, the term “electrode” or “wiring” can include the case where a plurality of “electrodes” or “wirings” is formed in an integrated manner.

Functions of a “source” and a “drain” are sometimes interchanged with each other when a transistor of opposite polarity is used or when the direction of current flowing is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.

Note that the term “electrically connected” in this specification and the like includes the case where components are connected through an “object having any electric function”. There is no particular limitation on an object having any electric function as long as electric signals can be transmitted and received between components that are connected through the object.

Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions, as well as an electrode and a wiring.

Since the off-state current of a transistor including an oxide semiconductor is extremely small, stored data can be held for an extremely long period when the transistor is used. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be held for a long period even when power is not supplied (note that the potential is preferably fixed).

Further, a semiconductor device according to the disclosed invention does not need high voltage for data writing and does not have the problem of element deterioration. For example, unlike a conventional nonvolatile memory, it is not necessary to inject and extract electrons into and from a floating gate, and thus a problem such as deterioration of a gate insulating layer does not arise at all. That is, the semiconductor device according to the disclosed invention has no limitation on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, since data is written by turning on or off the transistor, high-speed operation can be easily realized. Additionally, there is an advantage in that operation for erasing data is not needed.

When a transistor which includes a material other than an oxide semiconductor and can operate at sufficiently high speed is used as a reading transistor in combination with a transistor which includes an oxide semiconductor and is used as a writing transistor, a semiconductor device can perform operation (e.g., data reading) at sufficiently high speed. Further, a transistor including a material other than an oxide semiconductor can favorably realize a variety of circuits (e.g., a logic circuit or a driver circuit) which needs to be able to operate at high speed.

A semiconductor device having a novel feature can be realized by being provided with both the transistor including a material other than an oxide semiconductor (in other words, a transistor capable of operating at sufficiently high speed) and the transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small).

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A-1, 1A-2, and 1B are circuit diagrams of a semiconductor device.

FIGS. 2A and 2B are circuit diagrams of a semiconductor device.

FIG. 3 is a timing chart.

FIG. 4 is a circuit diagram of a semiconductor device.

FIGS. 5A and 5B are a cross-sectional view and a plan view of a semiconductor device.

FIGS. 6A to 6D are cross-sectional views illustrating a manufacturing process of a semiconductor device.

FIGS. 7A to 7C are cross-sectional views illustrating a manufacturing process of a semiconductor device.

FIGS. 8A to 8D are cross-sectional views illustrating a manufacturing process of a semiconductor device.

FIGS. 9A to 9C are cross-sectional views illustrating a manufacturing process of a semiconductor device.

FIGS. 10A to 10F each illustrate an electronic device including a semiconductor device.

FIG. 11 is a graph showing characteristics of a transistor including an oxide semiconductor.

FIG. 12 is a circuit diagram of an element for evaluating characteristics of a transistor including an oxide semiconductor.

FIG. 13 is a timing chart for an element for evaluating characteristics of a transistor including an oxide semiconductor.

FIG. 14 is a graph showing characteristics of a transistor including an oxide semiconductor.

FIG. 15 is a graph showing characteristics of a transistor including an oxide semiconductor.

FIG. 16 is a graph showing characteristics of a transistor including an oxide semiconductor.

BEST MODE FOR CARRYING OUT THE INVENTION

Examples of embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and the scope thereof. Therefore, the present invention should not be interpreted as being limited to the description in the following embodiments.

Note that the position, size, range, or the like of each component illustrated in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited by the position, size, range, or the like as disclosed in the drawings and the like.

Note that ordinal numbers such as “first”, “second”, and “third” in this specification and the like are used in order to avoid confusion among components, and the terms do not limit the components numerically.

Embodiment 1

In this embodiment, a circuit configuration and an operation of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. 1A-1, 1A-2, and 1B. Note that in some circuit diagrams, “OS” is written beside a transistor in order to indicate that the transistor includes an oxide semiconductor.

In a semiconductor device illustrated in FIG. 1A-1, a first wiring (1st Line) is electrically connected to a source electrode of a transistor 160. A second wiring (2nd Line) is electrically connected to a drain electrode of the transistor 160. A third wiring (3rd Line) is electrically connected to a source electrode of a transistor 162. A fourth wiring (4th Line) is electrically connected to a gate electrode of the transistor 162. Furthermore, a gate electrode of the transistor 160 and a drain electrode of the transistor 162 are electrically connected to one electrode of a capacitor 164. A fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 164.

Here, a transistor including an oxide semiconductor is used as the transistor 162 (a writing transistor). A transistor including an oxide semiconductor has a characteristic of a significantly small off-state current. For that reason, a potential of the gate electrode of the transistor 160 can be held for an extremely long period by turning off the transistor 162. By providing the capacitor 164, holding of charge applied to the gate electrode of the transistor 160 and reading of data held can be performed more easily.

Note that there is no particular limitation on the transistor 160 (a reading transistor). In terms of increasing the speed of reading data, it is preferable to use a transistor with high switching speed such as a transistor formed using single crystal silicon, for example. Note that a p-channel type transistor is used as the transistor 160.

Alternatively, a structure in which the capacitor 164 is not provided is also possible as illustrated in FIG. 1B.

The semiconductor device in FIG. 1A-1 utilizes a characteristic in which the potential of the gate electrode of the transistor 160 can be held, and can thus write, hold, and read data as follows.

First of all, writing and holding of data will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode of the transistor 160 and to the capacitor 164. That is, predetermined charge is supplied to the gate electrode of the transistor 160 (writing). Here, one of two kinds of charges providing different potentials is supplied (hereinafter, a charge providing a low potential is referred to as charge Q_(L) and a charge providing a high potential is referred to as charge Q_(H)). Note that three or more kinds of charges providing different potentials may be supplied in order to improve storage capacity. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, so that the transistor 162 is turned off. Thus, the charge supplied to the gate electrode of the transistor 160 is held (holding).

Since the off-state current of the transistor 162 is significantly small, the charge of the gate electrode of the transistor 160 is held for a long time.

Next, reading of data will be described. When an appropriate potential (a reading potential) is supplied to the fifth wiring while a predetermined potential (a constant potential) is supplied to the first wiring, the potential of the second wiring varies depending on the amount of charge held at the gate electrode of the transistor 160. That is, the conductance of the transistor 160 is controlled by the charge held at the gate electrode of the transistor 160 (which can also be referred to as a node FG).

In general, when the transistor 160 is a p-channel type transistor, an apparent threshold voltage V_(th) _(—) _(H) in the case where Q_(H) is supplied to the gate electrode of the transistor 160 is lower than an apparent threshold voltage V_(th) _(—) _(L) in the case where Q_(L) is supplied to the gate electrode of the transistor 160. For example, in the case where Q_(L) is supplied in writing, when the potential of the fifth wiring is V₀ (a potential intermediate between V_(th) _(—) _(H) and V_(th) _(—) _(L)), the transistor 160 is turned on. In the case where Q_(H) is supplied in writing, even when the potential of the fifth wiring is V₀, the transistor 160 remains off. Therefore, the data held can be read by measuring the potential of the second wiring. In the case where memory cells are arrayed to be used, fifth wirings of memory cells that are not a target for reading are supplied with a high potential at which the transistors 160 are turned off regardless of the state of the gate electrodes.

Next, rewriting of data will be described. Rewriting of data is performed in a manner similar to that of the writing and holding of data. In other words, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, so that the transistor 162 is turned on. Accordingly, the potential of the third wiring (a potential for new data) is supplied to the gate electrode of the transistor 160 and to the capacitor 164. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, so that the transistor 162 is turned off. Accordingly, charge for new data is supplied to the gate electrode of the transistor 160.

In the semiconductor device according to one embodiment of the disclosed invention, data can be directly rewritten by overwriting data as described above. Therefore, extraction of charge from a floating gate with the use of a high voltage which is necessary for a flash memory or the like is not needed, and thus a decrease in operation speed due to erasing operation can be suppressed. In other words, high-speed operation of the semiconductor device can be realized.

Note that the drain electrode (or the source electrode) of the transistor 162 is electrically connected to the gate electrode of the transistor 160 and thus has a function similar to that of a floating gate of a floating gate transistor used for a nonvolatile memory element. A portion where the drain electrode (or the source electrode) of the transistor 162 is electrically connected to the gate electrode of the transistor 160 is called a node FG in some cases. When the transistor 162 is turned off, the node FG can be regarded as being embedded in an insulator and thus charge is held at the node FG. The off-state current of the transistor 162 including an oxide semiconductor is smaller than or equal to 1/100000 of the off-state current of a transistor including a silicon semiconductor or the like; thus, loss of the charge accumulated in the node FG due to leakage in the transistor 162 is negligible. That is, with the transistor 162 including an oxide semiconductor, a nonvolatile memory device which can hold data without being supplied with power can be realized.

For example, when the off-state current of the transistor 162 at room temperature (25° C.) is 10 zA (1 zA (zeptoampere) is 1×10⁻²¹ A) or less and the capacitance of the capacitor 164 is approximately 10 fF, data can be held for 10⁴ seconds or longer. It is needless to say that the holding time depends on transistor characteristics and capacitance.

Further, the semiconductor device according to one embodiment of the disclosed invention does not have the problem of deterioration of a gate insulating film (tunnel insulating film), which is a problem of a conventional floating gate transistor. That is, the problem of deterioration of a gate insulating film due to injection of electrons into a floating gate, which is a conventional problem, can be solved. This means that there is no limit on the number of write cycles in principle. Furthermore, a high voltage needed for writing or erasing in a conventional floating gate transistor is not necessary.

Components such as transistors in the semiconductor device in FIG. 1A-1 can be regarded as including resistors and capacitors as illustrated in FIG. 1A-2. That is, in FIG. 1A-2, the transistor 160 and the capacitor 164 are each regarded as including a resistor and a capacitor. R1 and C1 denote the resistance and the capacitance of the capacitor 164, respectively. The resistance R1 corresponds to the resistance of the insulating layer included in the capacitor 164. R2 and C2 denote the resistance and the capacitance of the transistor 160, respectively. The resistance R2 corresponds to the resistance of the gate insulating layer at the time when the transistor 160 is turned on. The capacitance C2 corresponds to a so-called gate capacitance (a capacitance formed between the gate electrode and the source or drain electrode).

A charge holding period (also referred to as a data holding period) is determined mainly by the off-state current of the transistor 162 under the conditions where the gate leakage current of the transistor 162 is sufficiently small and R1 and R2 satisfy R1≧ROS (R1 is greater than or equal to ROS) and R2≧ROS (R2 is greater than or equal to ROS), where ROS is the resistance (also referred to as effective resistance) between the source electrode and the drain electrode in a state where the transistor 162 is turned off.

On the other hand, in the case where the above conditions are not satisfied, it is difficult to secure a sufficient holding period even if the off-state current of the transistor 162 is sufficiently small. This is because a leakage current other than the off-state current of the transistor 162 (e.g., a leakage current generated between the source electrode and the gate electrode) is large. Accordingly, it can be said that the semiconductor device disclosed in this embodiment preferably satisfies the above relationships of R1≧ROS (R1 is greater than or equal to ROS) and R2≧ROS (R2 is greater than or equal to ROS).

Meanwhile, it is desirable that C1 and C2 satisfy C1≧C2 (C1 is greater than or equal to C2). This is because if C1 is large, when the potential of the node FG is controlled by the fifth wiring, the potential of the fifth wiring can be efficiently supplied to the node FG and the difference between potentials supplied to the fifth wiring (e.g., a reading potential and a non-reading potential) can be kept small.

When the above relationships are satisfied, a more favorable semiconductor device can be realized. Note that R1 and R2 depend on the gate insulating layer of the transistor 160 and the insulating layer of the capacitor 164. The same applies to C1 and C2. Therefore, the material, the thickness, and the like of the gate insulating layer are preferably set as appropriate to satisfy the above relationships.

In the semiconductor device described in this embodiment, the node FG has a function similar to a floating gate of a floating gate transistor of a flash memory or the like, but the node FG of this embodiment has a feature which is essentially different from that of the floating gate of the flash memory or the like.

In the case of a flash memory, since a high potential is applied to a control gate, it is necessary to keep a proper distance between cells in order to prevent the potential of the control gate from affecting a floating gate of an adjacent cell. This is one factor inhibiting higher integration of the semiconductor device. The factor is attributed to a basic principle of a flash memory, in which a tunneling current is generated by applying a high electric field.

On the other hand, the semiconductor device according to this embodiment is operated by switching of a transistor including an oxide semiconductor and does not use the above-described principle of charge injection by a tunneling current. That is, a high electric field for charge injection is not necessary, unlike a flash memory. Accordingly, it is not necessary to consider an influence of a high electric field from a control gate on an adjacent cell, and this facilitates higher integration.

In addition, the semiconductor device according to this embodiment is advantageous over a flash memory also in that a high electric field is not necessary and a large peripheral circuit (such as a step-up circuit) is not necessary. For example, the highest voltage applied to the memory cell according to this embodiment (the difference between the highest potential and the lowest potential applied to respective terminals of the memory cell at the same time) can be 5 V or less, preferably 3 V or less, in each memory cell in the case where data of two stages (one bit) is written.

In the case where the relative permittivity ∈r1 of the insulating layer included in the capacitor 164 is different from the relative permittivity ∈2 of the insulating layer included in the transistor 160, it is easy to satisfy C1≧C2 (C1 is greater than or equal to C2) while satisfying 2·S2≦S1 (2·S2 is greater than or equal to S1), desirably S2≧S1 (S2 is greater than or equal to S1), where S1 is the area of the insulating layer included in the capacitor 164 and S2 is the area of the insulating layer forming a gate capacitor of the transistor 160. In other words, C1 can easily be made greater than or equal to C2 while the area of the insulating layer included in the capacitor 164 is made small. Specifically, for example, a film including a high-k material such as hafnium oxide or a stack of a film including a high-k material such as hafnium oxide and a film including an oxide semiconductor is used for the insulating layer included in the capacitor 164 so that ∈r1 can be set to 10 or more, preferably 15 or more, and silicon oxide is used for the insulating layer forming the gate capacitor so that ∈r2 can be set to approximately 3 to 4.

A combination of such structures enables further higher integration of the semiconductor device according to one embodiment of the disclosed invention.

Note that in addition to the increase in the degree of integration, a multilevel technique can be employed to increase the storage capacity of the semiconductor device. For example, three or more levels of data are written to one memory cell, whereby the storage capacity can be increased as compared to the case where two-level (one-bit) data is written. The multilevel technique can be achieved by, for example, supplying charge Q providing a potential to the gate electrode of the transistor 160, in addition to charge Q_(L) providing a low potential and charge Q_(H) providing a high potential as described above. In this case, enough storage capacity can be ensured even in a circuit structure with a relatively large scale (e.g., 15 F² to 50 F²; F is the minimum feature size).

Application Example 1

Next, a more specific circuit configuration to which the circuit illustrated in FIGS. 1A-1, 1A-2, and 1B is applied and an operation thereof will be described with reference to FIGS. 2A and 2B, FIG. 3, and FIG. 4. Note that the case where an n-channel type transistor is used as a writing transistor (the transistor 162) and a p-channel type transistor is used as a reading transistor (the transistor 160) will be described below as an example.

FIGS. 2A and 2B are an example of a circuit diagram of a semiconductor device including (m×n) memory cells 170. The configuration of the memory cells 170 in FIG. 2A is similar to that in FIG. 1A-1. That is, the second wiring in FIG. 1A-1 corresponds to a read bit line D in FIG. 2B; the third wiring in FIG. 1A-1, a write bit line OSS in FIG. 2B; the fourth wiring in FIG. 1A-1, a write word line OSG in FIG. 2B; and the fifth wiring in FIG. 1A-1, a write and read word line C in FIG. 2B. Note that a source line SL which is the first wiring in FIG. 1A-1 is omitted in FIG. 2A.

The semiconductor device in FIG. 2A includes m (m is an integer greater than or equal to 2) write word lines OSG, m write and read word lines C, n (n is an integer greater than or equal to 2) write bit lines OSS, n read bit lines D, a memory cell array having the memory cells 170 arranged in a matrix of m (rows) (in the vertical direction)×n (columns) (in the horizontal direction), a step-up circuit 180, a first driver circuit 190 connected to the n write bit lines OSS and the n read bit lines D, and a second driver circuit 192 connected to the m write word lines OSG and the m write and read word lines C.

In addition, a data input terminal DIN, a data output terminal DOUT, an address selection signal terminal A1, and the like are connected to the first driver circuit 190. The data input terminal DIN is a terminal to which data to be written to columns of the memory cells 170 are input, and the data output terminal DOUT is a terminal from which data written to columns of the memory cells are output. In some cases, a plurality of data input terminals DIN and a plurality of data output terminals DOUT may be provided depending on the circuit configuration of the first driver circuit 190. Note that the data input terminal DIN and the data output terminal DOUT may be a single common terminal. The address selection signal terminal A1 is a terminal to which a signal for selecting a column address of the memory cells is input. In some cases, a plurality of address selection signal terminals A1 may be provided depending on the number of columns of the memory cells or the circuit configuration of the first driver circuit 190.

Furthermore, an address selection signal terminal A2 is connected to the second driver circuit 192. The address selection signal terminal A2 is a terminal to which a signal for selecting a row address of memory cells is input. In some cases, a plurality of address selection signal terminals A2 may be provided depending on the number of rows of memory cells or the circuit configuration of the second driver circuit 192.

The semiconductor device illustrated in FIG. 2A determines whether to perform a writing operation or a reading operation, in accordance with a write enable signal which is input from a write enable signal input terminal WE and a read enable signal which is input from a read enable signal input terminal RE. Depending on the operation determined, the semiconductor device controls a signal to be output to the write word lines OSG, the write and read word lines C, the write bit lines OSS, or the read bit lines D. For example, the semiconductor device selects a writing operation when a high potential is input to the write enable signal input terminal WE, and selects a reading operation when a high potential is input to the read enable signal input terminal RE. Note that the relationship between the operation selected and the potential is not limited to this example.

The step-up circuit 180 is connected to the second driver circuit 192 through a wiring VHL and is configured to step up a constant potential (e.g., a power supply potential VDD) which is input from a step-up circuit input terminal UC and to output a potential (VH) higher than the constant potential to the second driver circuit 192. In order to prevent a potential written to the node FG of the memory cell 170 from being decreased by the threshold voltage (V_(th) _(—) _(Os)) of the writing transistor, the potential of the write word line OSG should be set higher than the sum of the potential of the write bit line OSS and V_(th) _(—) _(OS). Thus, for example, when the power supply potential VDD is written to the node FG, VH is set higher than or equal to (VDD+V_(th) _(—) _(Os)). Note that if a decrease in the potential written to the node FG by V_(th) _(—) _(Os) does not cause any problem, the step-up circuit 180 is not necessarily provided. In this specification, the threshold voltage of a transistor refers to a potential difference between the gate electrode and the source electrode (or the drain electrode) at the time when the transistor is switched from an on state to an off state.

Data writing, holding, and reading in the semiconductor device illustrated in FIGS. 2A and 2B are basically similar to those in the case of FIGS. 1A-1, 1A-2, and 1B. FIG. 3 is an example of a timing chart for the writing and reading operations of the semiconductor device in FIGS. 2A and 2B. WE, OSG, and the like in the timing chart denote the lines or terminals to which the potentials in the timing chart are supplied. Lines having a similar function are distinguished by “_(—)1”, “_(—)2”, and the like added to the end of their names. Note that for the sake of simplicity, the semiconductor device described here is an example where the memory cells 170 are arranged in 2 (rows)×2 (columns), but the disclosed invention is not limited to this example.

The timing chart in FIG. 3 shows the relationship among the potentials of the lines in the case where, in a writing period, data “1” is written to the memory cell in the first row and the first column, data “0” is written to the memory cell in the first row and the second column, data “0” is written to the memory cell in the second row and the first column, and data “1” is written to the memory cell in the second row and the second column, and then, in a reading period, the data written are read.

Note that, although the case where either the potential VDD or a ground potential GND is supplied to the node FG is described here as an example, the relationship among potentials supplied to the node FG is not limited to this example. Note also that data that is held when the potential VDD is supplied to the node FG is referred to as data “1”, and data that is held when the ground potential GND is supplied to the node FG is referred to as data “0”. Although not illustrated in FIG. 3, the potential of the source line SL is set to VDD or a potential (VDDL) which is lower than VDD to some extent. Note that the potential of the source line SL may be temporarily changed unless the operation is interfered with.

In the writing period, a condition where data can be written to the memory cells is produced by setting WE at a high potential and RE at a low potential. Note that REB in FIG. 3 is a signal obtained by inverting a signal which is input from RE.

In order to write data “1” to the memory cell in the first row and the first column and data “0” to the memory cell in the first row and the second column, OSS_1 is set at VDD and OSS_2 is set at GND at the timing of selection of the first row, that is, at the time when the potential of OSG_1 becomes high and the potential of C_1 becomes low. In addition, in order to write data “0” to the memory cell in the second row and the first column and data “1” to the memory cell in the second row and the second column, OSS_1 is set at GND and OSS_2 is set at VDD at the timing of selection of the second row, that is, at the time when the potential of OSG_2 becomes high and the potential of C_2 becomes low. Note that in the case of using the step-up circuit 180, the high potential of OSG_1 and OSG_2 is a step-up circuit output potential VH which is higher than or equal to (VDD+V_(th) _(—) _(OS)).

Note that the period for inputting a signal to OSS (OSS_1 and OSS_2) is preferably set as long as or longer than the period for inputting a signal to OSG (OSG_1 and OSG_2). This is because there is a possibility that writing to the memory cells 170 may be insufficient if the potential of OSS falls before that of OSG does. Alternatively, the input of a signal to OSS may be delayed relative to the input of a signal to OSG by, for example, connecting a delay circuit to OSS. Note that the potentials of D_1 and D_2 are not an issue in the writing period (the potentials may be either a high potential or a low potential).

In the reading period, a condition where data can be read from the memory cells is produced by setting WE at a low potential and RE at a high potential. The second driver circuit 192 outputs a row selection signal based on an address input signal to OSG (OSG_1 and OSG_2) and C (C_1 and C_2). C_1 and C_2 are at a low potential when the memory cell rows are selected and at a high potential when not selected, and OSG_1 and OSG_2 are at a low potential regardless of whether the memory cell rows are selected or not. Note that the potentials of OSS_1 and OSS_2 are not an issue at the time of reading.

By the above operation, potentials based on data held in memory cells of a row selected are supplied to D_1 and D_2. In the case where data “1” is written in a memory cell selected, the transistor 160 is turned off; thus, GND is supplied to D_1 or D_2. In the case where data “0” is written in a memory cell selected, the transistor 160 is turned on; thus, VDD is supplied to D_1 or D_2. Note that at the time of writing, D_1 and D_2 are at VDD or at high impedance without being connected to either VDD or GND.

Next, an output potential obtained in the case where a circuit illustrated in FIG. 4 is used as an example of a reading circuit will be described. In the reading period, RE is at a high potential and a clocked inverter is operable. Thus, when VDD is supplied to D_1 or D_2, a high potential is input to the clocked inverter and the potential of the output terminal DOUT becomes low. When GND is supplied to D_1 or D_2, a low potential is input to the clocked inverter and the potential of the output terminal DOUT becomes high.

When reading is performed in the semiconductor device in FIGS. 2A and 2B, memory cells in a non-selected row need to be turned off. If n-channel type transistors are used as reading transistors, when the potential of a gate electrode of a reading transistor becomes higher than the threshold voltage of the reading transistor, all the memory cells cannot always be turned off even by setting the write and read word lines C at 0 V. Therefore, a negative potential needs to be supplied to a write and read word line C of a non-selected row.

On the other hand, in the semiconductor device illustrated in FIGS. 2A and 2B, p-channel type transistors are used as the reading transistors. Therefore, memory cells in a non-selected row can be turned off by setting the write and read word line C of the non-selected row at a high potential. Accordingly, the memory cells do not require a power source which generates a negative potential. As a result, power consumption can be reduced and the semiconductor device can be downsized.

Note that the operation method, the operation voltage, and the like for the semiconductor device of an embodiment of the disclosed invention are not limited to those described above and can be changed appropriately in accordance with an embodiment as long as the semiconductor device can operate.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Embodiment 2

In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIGS. 5A and 5B, FIGS. 6A to 6D, FIGS. 7A to 7C, FIGS. 8A to 8D, and FIGS. 9A to 9C.

<Cross-Sectional Structure and Planar Structure of Semiconductor Device>

FIGS. 5A and 5B illustrate an example of a structure of a semiconductor device. FIG. 5A is a cross-sectional view of the semiconductor device, and FIG. 5B is a plan view of the semiconductor device. Here, FIG. 5A corresponds to a cross section along line A1-A2 and line B1-B2 in FIG. 5B. The semiconductor device illustrated in FIGS. 5A and 5B includes, in a lower portion, a transistor 160 including a first semiconductor material, and in an upper portion, a transistor 162 including a second semiconductor material. Here, a p-channel type transistor is used as the transistor 160. In addition, the first semiconductor material and the second semiconductor material are preferably different materials. For example, the first semiconductor material can be a semiconductor material (such as silicon) other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. The semiconductor material other than an oxide semiconductor may be, for example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like and is preferably a single crystal semiconductor. A transistor including such a semiconductor material can operate at sufficiently high speed; thus, reading of data stored and the like can be performed at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time owing to its characteristics.

Since the technical nature of the disclosed invention is to use a semiconductor material with which off-state current can be sufficiently decreased, such as an oxide semiconductor, in the transistor 162 so that data can be stored, it is not necessary to limit a specific structure of the semiconductor device, such as a material of the semiconductor device or a structure of the semiconductor device, to the structure described here.

The transistor 160 in FIGS. 5A and 5B includes a channel formation region 116 provided in a substrate 100 including a semiconductor material (such as silicon), impurity regions 120 provided such that the channel formation region 116 is sandwiched therebetween, metal compound regions 124 in contact with the impurity regions 120, a gate insulating layer 108 provided over the channel formation region 116, and a gate electrode 110 provided over the gate insulating layer 108. Note that a transistor whose source electrode and drain electrode are not illustrated in a drawing may also be referred to as a transistor for the sake of convenience. Further, in such a case, in description of a connection of a transistor, a source region and a source electrode may be collectively referred to as a source electrode, and a drain region and a drain electrode may be collectively referred to as a drain electrode. That is, in this specification, the term “source electrode” may include a source region.

Further, an element isolation insulating layer 106 is formed over the substrate 100 so as to surround the transistor 160, and an insulating layer 128 and an insulating layer 130 are formed to cover the transistor 160. Note that in order to realize higher integration, the transistor 160 preferably has a structure without a sidewall insulating layer as illustrated in FIGS. 5A and 5B. On the other hand, in the case where characteristics of the transistor 160 have priority, a sidewall insulating layer may be provided on a side surface of the gate electrode 110, and the impurity regions 120 may include a region having a different impurity concentration.

The transistor 162 in FIGS. 5A and 5B includes a source electrode 142 a and a drain electrode 142 b provided over the insulating layer 130, an oxide semiconductor layer 144 electrically connected to the source electrode 142 a and the drain electrode 142 b, a gate insulating layer 146 covering the source electrode 142 a, the drain electrode 142 b, and the oxide semiconductor layer 144, a gate electrode 148 a provided over the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 144, an insulating layer 143 a between the source electrode 142 a and the oxide semiconductor layer 144 in a region overlapping with the gate electrode 148 a, and an insulating layer 143 b between the drain electrode 142 b and the oxide semiconductor layer 144 in a region overlapping with the gate electrode 148 a. Although the insulating layer 143 a and the insulating layer 143 b are preferably provided in order to reduce the capacitance between the source or drain electrodes and the gate electrode, a structure in which the insulating layer 143 a and the insulating layer 143 b are not provided is also possible.

Here, the oxide semiconductor layer 144 is preferably an oxide semiconductor layer which is purified by sufficiently removing an impurity such as hydrogen therefrom or by sufficiently supplying oxygen thereto. Specifically, the hydrogen concentration of the oxide semiconductor layer 144 is 5×10¹⁹ atoms/cm³ or less, preferably 5×10¹⁸ atoms/cm³ or less, more preferably 5×10¹⁷ atoms/cm³ or less, for example. Note that the above hydrogen concentration of the oxide semiconductor layer 144 is measured by secondary ion mass spectrometry (SIMS). The concentration of carriers generated due to a donor such as hydrogen in the oxide semiconductor layer 144, in which hydrogen is reduced to a sufficiently low concentration so that the oxide semiconductor layer is purified and in which defect states in an energy gap due to oxygen deficiency are reduced by sufficiently supplying oxygen as described above, is less than 1×10¹²/cm³, preferably less than 1×10¹¹/cm³, more preferably less than 1.45×10¹⁰/cm³. For example, the off-state current (per unit channel width (1 μm), here) at room temperature (25° C.) is 100 zA (1 zA (zeptoampere) is 1×10⁻²¹ A) or less, preferably 10 zA or less. In this manner, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, the transistor 162 which has extremely favorable off-state current characteristics can be obtained.

Although the oxide semiconductor layer 144 processed in an island shape is used in the transistor 162 of FIGS. 5A and 5B in order to suppress leakage caused among elements due to miniaturization, an oxide semiconductor layer not processed in an island shape may be used. When an oxide semiconductor layer is not processed in an island shape, the oxide semiconductor layer 144 can be prevented from being contaminated by etching during processing.

A capacitor 164 in FIGS. 5A and 5B includes the source electrode 142 a, the oxide semiconductor layer 144, the gate insulating layer 146, and an electrode 148 b. In other words, the source electrode 142 a functions as one electrode of the capacitor 164, and the electrode 148 b functions as the other electrode of the capacitor 164.

Note that in the capacitor 164 of FIGS. 5A and 5B, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked, whereby insulation between the source electrode 142 a and the electrode 148 b can be sufficiently secured. It is needless to say that the capacitor 164 without including the oxide semiconductor layer 144 may be employed in order to secure sufficient capacitance. Alternatively, the capacitor 164 including an insulating layer that is formed in a manner similar to that of the insulating layer 143 a may be employed. Furthermore, in the case where no capacitor is needed, a structure in which the capacitor 164 is not provided is also possible.

Note that in the transistor 162 and the capacitor 164, the source electrode 142 a and the drain electrode 142 b preferably have tapered end portions. The source electrode 142 a and the drain electrode 142 b preferably have tapered end portions because the coverage thereof with the oxide semiconductor layer 144 can be improved and disconnection thereof can be prevented. Here, the taper angle is 30° to 60°, for example. Note that the “taper angle” means an angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode 142 a) when observed from a direction perpendicular to a cross section thereof (a plane perpendicular to the substrate surface).

In this embodiment, the transistor 162 and the capacitor 164 are provided so as to overlap with the transistor 160. By employing such a planar layout, higher integration can be realized. For example, given that the minimum feature size is F, the area occupied by a memory cell can be approximately 15 F² to 25 F².

An insulating layer 150 is provided over the transistor 162 and the capacitor 164, and an insulating layer 152 is provided over the insulating layer 150. Then, an electrode 154 is provided in an opening formed in the gate insulating layer 146, the insulating layer 150, the insulating layer 152, and the like, and a wiring 156 is formed over the insulating layer 152 so as to be connected to the electrode 154. Although the drain electrode 142 b and the wiring 156 are connected by the electrode 154 in FIGS. 5A and 5B, the disclosed invention is not limited to this structure. For example, the wiring 156 may be in direct contact with the drain electrode 142 b.

<Method for Manufacturing Semiconductor Device>

Next, an example of a method for manufacturing the semiconductor device will be described. First, a method for manufacturing the transistor 160 in the lower portion will be described below with reference to FIGS. 6A to 6D and FIGS. 7A to 7C; then, a method for manufacturing the transistor 162 in the upper portion and the capacitor 164 will be described with reference to FIGS. 8A to 8D and FIGS. 9A to 9C.

<Method for Manufacturing Transistor in Lower Portion>

First, the substrate 100 including a semiconductor material is prepared (see FIG. 6A). A single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon, silicon carbide, or the like, a compound semiconductor substrate of silicon germanium or the like, an SOI substrate, or the like can be used as the substrate 100 including a semiconductor material. Here, an example of the case where a single crystal silicon substrate is used as the substrate 100 including a semiconductor material is described. Note that the term “SOI substrate” generally means a substrate where a silicon semiconductor layer is provided over an insulating surface. In this specification and the like, the term “SOI substrate” also means a substrate where a semiconductor layer including a material other than silicon is provided over an insulating surface. That is, a semiconductor layer included in the “SOI substrate” is not limited to a silicon semiconductor layer. Moreover, the SOI substrate can be a substrate having a structure where a semiconductor layer is provided over an insulating substrate such as a glass substrate with an insulating layer interposed therebetween.

It is preferable that a single crystal semiconductor substrate of silicon or the like be particularly used as the substrate 100 including a semiconductor material because the speed of reading operation of the semiconductor device can be increased.

First, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed over the substrate 100 (see FIG. 6A). As the protective layer 102, an insulating layer formed using a material such as silicon oxide, silicon nitride, silicon oxynitride, or the like can be used, for example. Note that before or after this step, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100 in order to control the threshold voltage of the transistor. When the semiconductor material included in the substrate 100 is silicon, phosphorus, arsenic, or the like can be used as the impurity imparting n-type conductivity. Boron, aluminum, gallium, or the like can be used as the impurity imparting p-type conductivity.

Next, part of the substrate 100 in a region not covered with the protective layer 102 (i.e., in an exposed region) is removed by etching using the protective layer 102 as a mask. Thus, a semiconductor region 104 isolated from other semiconductor regions is formed (see FIG. 6B). As the etching, dry etching is preferably performed, but wet etching may be performed. An etching gas or an etchant can be selected as appropriate depending on a material to be etched.

Then, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in a region overlapping with the semiconductor region 104 is selectively removed; thus, the element isolation insulating layer 106 is formed (see FIG. 6C). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, or the like. As a method for removing the insulating layer, any of etching treatment, polishing treatment such as chemical mechanical polishing (CMP), and the like can be employed. Note that the protective layer 102 is removed after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106.

Next, an insulating layer is formed over a surface of the semiconductor region 104, and a layer including a conductive material is formed over the insulating layer.

The insulating layer is processed into a gate insulating layer later and can be formed by, for example, heat treatment (thermal oxidation treatment, thermal nitridation treatment, or the like) of the surface of the semiconductor region 104. Instead of heat treatment, high-density plasma treatment may be employed. The high-density plasma treatment can be performed using, for example, a mixed gas of any of a rare gas such as He, Ar, Kr, or Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, and the like. It is needless to say that the insulating layer may be formed by a CVD method, a sputtering method, or the like. The insulating layer preferably has a single-layer structure or a stacked-layer structure with a film including silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi_(x)O_(y) (x>0, y>0)), hafnium silicate to which nitrogen is added (HfSi_(x)O_(y)N_(z) (x>0, y>0, z>0)), hafnium aluminate to which nitrogen is added (HfAl_(x)O_(y)N_(z) (x>0, y>0, z>0)), or the like. The insulating layer can have a thickness of 1 nm to 100 nm, preferably, 10 nm to 50 nm, for example.

The layer including a conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The layer including a conductive material may be formed using a semiconductor material such as polycrystalline silicon. There is no particular limitation on the method for forming the layer including a conductive material, and a variety of film formation methods such as an evaporation method, a CVD method, a sputtering method, or a spin coating method can be employed. Note that this embodiment shows an example of the case where the layer including a conductive material is formed using a metal material.

After that, the insulating layer and the layer including a conductive material are selectively etched; thus, the gate insulating layer 108 and the gate electrode 110 are formed (see FIG. 6C).

Next, an impurity element such as boron (B) or aluminum (Al) is added to the semiconductor region 104, whereby the channel formation region 116 and the impurity regions 120 are formed (see FIG. 6D). Here, the concentration of the impurity added can be set as appropriate; the concentration is preferably set high when a semiconductor element is highly miniaturized.

Note that a sidewall insulating layer may be formed around the gate electrode 110, and impurity regions to which the impurity element is added at a different concentration may be formed.

Next, a metal layer 122 is formed so as to cover the gate electrode 110, the impurity regions 120, and the like (see FIG. 7A). The metal layer 122 can be formed by a variety of film formation methods such as a vacuum evaporation method, a sputtering method, and a spin coating method. The metal layer 122 is preferably formed using a metal material which forms a low-resistance metal compound by reacting with the semiconductor material included in the semiconductor region 104. Examples of such metal materials are titanium, tantalum, tungsten, nickel, cobalt, platinum, and the like.

Next, heat treatment is performed so that the metal layer 122 reacts with the semiconductor material. Thus, the metal compound regions 124 that are in contact with the impurity regions 120 are formed (see FIG. 7A). Note that when the gate electrode 110 is formed using polycrystalline silicon or the like, a metal compound region is also formed in a portion of the gate electrode 110 which is in contact with the metal layer 122.

As the heat treatment, irradiation with a flash lamp can be employed, for example. Although it is needless to say that another heat treatment method may be used, a method by which heat treatment can be achieved in an extremely short time is preferably used in order to improve the controllability of chemical reaction for formation of the metal compound. Note that the metal compound regions are formed by reaction of the metal material and the semiconductor material and have sufficiently high conductivity. The formation of the metal compound regions can properly reduce the electric resistance and improve element characteristics. Note that the metal layer 122 is removed after the metal compound regions 124 are formed.

Next, the insulating layer 128 and the insulating layer 130 are formed so as to cover the components formed in the above steps (see FIG. 7B). The insulating layer 128 and the insulating layer 130 can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or aluminum oxide. It is particularly preferable to use a low dielectric constant (low-k) material for the insulating layer 128 and the insulating layer 130 because capacitance due to overlap of electrodes or wirings can be sufficiently reduced. Note that a porous insulating layer with such a material may be employed as the insulating layer 128 and the insulating layer 130. The porous insulating layer has a lower dielectric constant than an insulating layer with high density and thus makes it possible to further reduce capacitance due to electrodes or wirings. Alternatively, the insulating layer 128 and the insulating layer 130 can be formed using an organic insulating material such as polyimide or acrylic. Note that although a stacked structure of the insulating layer 128 and the insulating layer 130 is used in this embodiment, an embodiment of the disclosed invention is not limited to this example. A single-layer structure or a stacked-layer structure including three or more layers can also be used.

Through the above steps, the transistor 160 is formed with the use of the substrate 100 including a semiconductor material (see FIG. 7B). A feature of the transistor 160 is that it can operate at high speed. With the use of that transistor as a reading transistor, data can be read at high speed.

Furthermore, because the transistor 160 is a p-channel type transistor, when used as a reading transistor, the memory cell does not require a power source which generates a negative potential for a reading operation; thus, power consumption can be reduced and the semiconductor device can be downsized. Further, operation can be performed at high speed as compared to the case of using a negative potential for reading.

After that, as treatment performed before the transistor 162 and the capacitor 164 are formed, CMP treatment of the insulating layer 128 and the insulating layer 130 is performed so that an upper surface of the gate electrode 110 is exposed (see FIG. 7C). As treatment for exposing the upper surface of the gate electrode 110, etching treatment, or the like can also be employed instead of CMP treatment; in order to improve characteristics of the transistor 162, surfaces of the insulating layer 128 and the insulating layer 130 are preferably made as flat as possible.

Note that before or after each of the above steps, a step of forming an electrode, a wiring, a semiconductor layer, an insulating layer, or the like may be further performed. For example, when the wiring has a multi-layer structure of a stacked-layer structure including insulating layers and conductive layers, a highly integrated semiconductor device can be realized.

<Method for Manufacturing Transistor in Upper Portion>

Next, a conductive layer is formed over the gate electrode 110, the insulating layer 128, the insulating layer 130, and the like, and the source electrode 142 a and the drain electrode 142 b are formed by selectively etching the conductive layer (see FIG. 8A).

The conductive layer can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. As a material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy including any of these elements as a component, or the like can be used. A material including one of manganese, magnesium, zirconium, beryllium, neodymium, or scandium or a combination of a plurality of these elements may be used.

The conductive layer may have a single-layer structure or a stacked-layer structure including two or more layers. For example, the conductive layer may have a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, or the like. Note that the conductive layer having a single-layer structure of a titanium film or a titanium nitride film has an advantage in that it can be easily processed into the source electrode 142 a and the drain electrode 142 b having a tapered shape.

The conductive layer may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), an indium oxide-tin oxide alloy (In₂O₃—SnO₂, which is abbreviated to ITO in some cases), an indium oxide-zinc oxide alloy (In₂O₃—ZnO), or any of these metal oxide materials including silicon or silicon oxide can be used.

The conductive layer is preferably etched such that the source electrode 142 a and the drain electrode 142 b are formed to have tapered end portions. Here, the taper angle is preferably 30° to 60°, for example. When the source electrode 142 a and the drain electrode 142 b are formed by etching so as to have tapered end portions, coverage of the source electrode 142 a and the drain electrode 142 b with the gate insulating layer 146 which is formed later can be improved and disconnection of the gate insulating layer 146 can be prevented.

The channel length (L) of the transistor in the upper portion is determined by a distance between lower edge portions of the source electrode 142 a and the drain electrode 142 b. Note that for light exposure for forming a mask in the case of manufacturing a transistor with a channel length (L) of less than 25 nm, light exposure is preferably performed with extreme ultraviolet light whose wavelength is several nanometers to several tens of nanometers, which is extremely short. The resolution of light exposure with extreme ultraviolet rays is high and the depth of focus is large. For these reasons, the channel length (L) of the transistor to be formed later can be set in the range of 10 nm to 1000 nm (1 μm), and the circuit can operate at higher speed. In addition, power consumption of the semiconductor device can be reduced by miniaturization.

Note that an insulating layer functioning as a base may be provided over the insulating layer 128 and the insulating layer 130. The insulating layer can be formed by a PVD method, a CVD method, or the like.

Next, the insulating layer 143 a is formed over the source electrode 142 a, and the insulating layer 143 b is formed over the drain electrode 142 b (see FIG. 8B). The insulating layer 143 a and the insulating layer 143 b can be formed by forming an insulating layer so as to cover the source electrode 142 a and the drain electrode 142 b and then by selectively etching the insulating layer. In addition, the insulating layer 143 a and the insulating layer 143 b are formed so as to overlap with part of a gate electrode which is formed later. With such insulating layers, capacitance between the gate electrode and the source or drain electrodes can be reduced.

The insulating layer 143 a and the insulating layer 143 b can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or aluminum oxide. It is particularly preferable to use a low dielectric constant (low-k) material for the insulating layer 143 a and the insulating layer 143 b because capacitance between the gate electrode and the source or drain electrodes can be sufficiently reduced. Note that a porous insulating layer with such a material may be employed as the insulating layer 143 a and the insulating layer 143 b. The porous insulating layer has a lower dielectric constant than an insulating layer with high density and thus makes it possible to further reduce capacitance between the gate electrode and the source or drain electrodes.

Note that although the insulating layers 143 a and 143 b are preferably provided for reduction in capacitance between the gate electrode and the source or drain electrodes, a structure in which the insulating layers are not provided is also possible.

Next, the oxide semiconductor layer 144 is formed by forming an oxide semiconductor layer so as to cover the source electrode 142 a and the drain electrode 142 b and then by selectively etching the oxide semiconductor layer (see FIG. 8C).

The oxide semiconductor layer contains at least one element selected from In, Ga, Sn, and Zn. For example, the oxide semiconductor layer can be formed using a four-component metal oxide such as In—Sn—Ga—Zn—O-based oxide semiconductor, a three-component metal oxide such as an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, or a Sn—Al—Zn—O-based oxide semiconductor, a two-component metal oxide such as an In—Zn—O-based oxide semiconductor, an In—Ga—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O—based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, or an In—Mg—O-based oxide semiconductor, an In—O-based oxide semiconductor, a Sn—O-based oxide semiconductor, a Zn—O-based oxide semiconductor, or the like. In addition, any of the above oxide semiconductors may contain an element other than In, Ga, Sn, and Zn, for example, SiO₂.

For example, an In—Ga—Zn—O-based oxide semiconductor means an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), and there is no limitation on the composition ratio thereof.

In particular, an In—Ga—Zn—O-based oxide semiconductor material has sufficiently high resistance when there is no electric field and thus off-state current can be sufficiently reduced. In addition, also having high field-effect mobility, the In—Ga—Zn—O-based oxide semiconductor material is suitable for a semiconductor material used in a semiconductor device.

As a typical example of the In—Ga—Zn—O-based oxide semiconductor material, an oxide semiconductor material represented by InGaO₃(ZnO)_(m) (m>0) is given. Using M instead of Ga, there is an oxide semiconductor material represented by InMO₃(ZnO)_(m) (m>0). Here, M denotes one or more metal elements selected from zinc (Zn), gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), or the like. For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, or the like. Note that the above-described compositions are derived from the crystal structures that the oxide semiconductor material can have and are mere examples.

As a target used for forming the oxide semiconductor layer by a sputtering method, a target having a composition ratio of In:Ga:Zn=1:x:y (x is greater than or equal to 0 and y is greater than or equal to 0.5 and less than or equal to 5) is preferably used. For example, a target having a composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:2 [molar ratio] or the like can be used. Furthermore, a target having a composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:1 [molar ratio] or a target having a composition ratio of In₂O₃:Ga₂O₃:ZnO=1:1:4 [molar ratio] can also be used.

In the case where an In—Zn—O-based material is used as an oxide semiconductor, a target therefore has a composition ratio of In:Zn=50:1 to 1:2 in an atomic ratio (In₂O₃:ZnO=25:1 to 1:4 in a molar ratio), preferably, In:Zn=20:1 to 1:1 in an atomic ratio (In₂O₃:ZnO=10:1 to 1:2 in a molar ratio), further preferably, In:Zn=15:1 to 1.5:1 in an atomic ratio (In₂O₃:ZnO=15:2 to 3:4 in a molar ratio). For example, in a target used for formation of an In—Zn—O-based oxide semiconductor which has an atomic ratio of In:Zn:O=X:Y:Z, the relation of Z>1.5X+Y is satisfied.

In this embodiment, an oxide semiconductor layer having an amorphous structure is formed by a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target.

The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more, and more preferably 99.9% or more. The use of the metal oxide target with high relative density makes it possible to form an oxide semiconductor layer having a dense structure.

The atmosphere in which the oxide semiconductor layer is formed is preferably a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically, argon) and oxygen. Specifically, it is preferable to use a high-purity gas atmosphere, for example, from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of 1 ppm or less (preferably, 10 ppb or less).

In forming the oxide semiconductor layer, for example, an object to be processed is held in a treatment chamber that is maintained under reduced pressure, and the object to be processed is heated to a temperature higher than or equal to 100° C. and lower than 550° C., preferably higher than or equal to 200° C. and lower than or equal to 400° C. Alternatively, the temperature of an object to be processed in forming the oxide semiconductor layer may be room temperature (25° C.±10° C.). Then, moisture in the treatment chamber is removed, a sputtering gas from which hydrogen, water, or the like is removed is introduced, and the above-described target is used; thus, the oxide semiconductor layer is formed. By forming the oxide semiconductor layer while heating the object to be processed, an impurity in the oxide semiconductor layer can be reduced. Moreover, damage due to sputtering can be reduced. In order to remove the moisture in the treatment chamber, it is preferable to use an entrapment vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, or the like can be used. A turbomolecular pump provided with a cold trap may be used. Since hydrogen, water, or the like can be removed from the treatment chamber evacuated with a cryopump or the like, the concentration of an impurity in the oxide semiconductor layer can be reduced.

For example, conditions for forming the oxide semiconductor layer can be set as follows: the distance between the object to be processed and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is an oxygen (100% oxygen) atmosphere, an argon (100% argon) atmosphere, or a mixed atmosphere of oxygen and argon. Note that a pulsed direct current (DC) power source is preferably used because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform. The thickness of the oxide semiconductor layer is set in the range of 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 10 nm. The use of the oxide semiconductor layer of such a thickness makes it possible to suppress a short channel effect which is caused by miniaturization. Note that the appropriate thickness of the oxide semiconductor layer differs depending on the oxide semiconductor material to be used, the intended use of the semiconductor device, or the like; therefore, the thickness can be determined as appropriate in accordance with the material, the intended use, or the like.

Note that before the oxide semiconductor layer is formed by a sputtering method, reverse sputtering in which plasma is generated with an argon gas introduced is preferably performed so that a material attached to a formation surface (e.g., a surface of the insulating layer 130) is removed. Here, the reverse sputtering is a method in which ions collide with a surface to be processed so that the surface is modified, in contrast to normal sputtering in which ions collide with a sputtering target. An example of a method for making ions collide with a surface to be processed is a method in which high-frequency voltage is applied to the surface side in an argon atmosphere so that plasma is generated near the object to be processed. Note that an atmosphere of nitrogen, helium, oxygen, or the like may be used instead of an argon atmosphere.

After that, heat treatment (first heat treatment) is preferably performed on the oxide semiconductor layer. Through the first heat treatment, excess hydrogen (including water or a hydroxyl group) in the oxide semiconductor layer can be removed, the structure of the oxide semiconductor layer can be ordered, and defect states in an energy gap can be reduced. For example, the temperature of the first heat treatment can be set higher than or equal to 300° C. and lower than 550° C., or higher than or equal to 400° C. and lower than or equal to 500° C.

For example, after an object to be processed is introduced into an electric furnace including a resistance heater or the like, the heat treatment can be performed at 450° C. for one hour in a nitrogen atmosphere. The oxide semiconductor layer is not exposed to the air during the heat treatment so that entry of water or hydrogen can be prevented.

The heat treatment apparatus is not limited to the electric furnace and may be an apparatus for heating an object to be processed by thermal radiation or thermal conduction from a medium such as a heated gas. For example, a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas that does not react with an object to be processed by heat treatment, for example, nitrogen or a rare gas such as argon is used.

For example, as the first heat treatment, GRTA treatment may be performed as follows. The object to be processed is put in a heated inert gas atmosphere, heated for several minutes, and taken out of the inert gas atmosphere. The GRTA treatment enables high-temperature heat treatment in a short time. Moreover, the GRTA treatment can be employed even when the temperature exceeds the upper temperature limit of the object to be processed. Note that the inert gas may be switched to a gas including oxygen during the treatment. This is because defect states in an energy gap caused by oxygen vacancies can be reduced by performing the first heat treatment in an atmosphere including oxygen.

Note that as the inert gas atmosphere, an atmosphere that contains nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen, or the like is preferably used. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

In any case, a transistor with extremely excellent characteristics can be obtained with the use of the oxide semiconductor layer which is an i-type (intrinsic) or substantially i-type oxide semiconductor layer obtained by reducing an impurity through the first heat treatment.

The above heat treatment (the first heat treatment) can also be referred to as dehydration treatment, dehydrogenation treatment, or the like because it has the effect of removing hydrogen, water, or the like. The dehydration treatment or the dehydrogenation treatment can be performed after the oxide semiconductor layer is formed, after the gate insulating layer is formed, or after a gate electrode is formed. Such dehydration treatment or dehydrogenation treatment may be performed once or plural times.

The etching of the oxide semiconductor layer may be performed either before the heat treatment or after the heat treatment. Dry etching is preferably used in terms of element miniaturization, but wet etching may be used. An etching gas or an etchant can be selected as appropriate depending on a material to be etched. Note that in the case where leakage in an element or the like does not cause a problem, the oxide semiconductor layer does not necessarily need to be processed in an island shape.

Next, the gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144. Then, over the gate insulating layer 146, the gate electrode 148 a is formed in a region overlapping with the oxide semiconductor layer 144, and the electrode 148 b is formed in a region overlapping with the source electrode 142 a (see FIG. 8D).

The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 is preferably formed so as to contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (HfSi_(x)O_(y) (x>0, y>0)), hafnium silicate to which nitrogen is added (HfSi_(x)O_(y)N_(z) (x>0, y>0, z>0)), hafnium aluminate to which nitrogen is added (HfAl_(x)O_(y)N_(z) (x>0, y>0, z>0)), or the like. The gate insulating layer 146 may have a single-layer structure or a stacked-layer structure. There is no particular limitation on the thickness of the gate insulating layer 146; the thickness is preferably small in order to ensure the operation of the transistor when the semiconductor device is miniaturized. For example, in the case of using silicon oxide, the thickness can be 1 nm to 100 nm, preferably 10 nm to 50 nm.

When the gate insulating layer is thin as described above, gate leakage due to a tunneling effect or the like becomes a problem. In order to solve the problem of gate leakage, the gate insulating layer 146 may be formed using a high dielectric constant (high-k) material such as hafnium oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi_(x)O_(y) (x>0, y>0)), hafnium silicate to which nitrogen is added (HfSi_(x)O_(y)N_(z) (x>0, y>0, z>0)), hafnium aluminate to which nitrogen is added (HfAl_(x)O_(y)N_(z) (x>0, y>0, z>0)). The use of a high-k material for the gate insulating layer 146 makes it possible to increase the thickness in order to suppress gate leakage as well as ensuring electrical properties. Note that a stacked-layer structure of a film including a high-k material and a film including any of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, and the like may also be employed.

After the gate insulating layer 146 is formed, second heat treatment is preferably performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is set in the range of 200° C. to 450° C., preferably 250° C. to 350° C. For example, the heat treatment may be performed at 250° C. for one hour in a nitrogen atmosphere. By the second heat treatment, variation in electrical characteristics of the transistor can be reduced. In the case where the gate insulating layer 146 contains oxygen, oxygen can be supplied to the oxide semiconductor layer 144 and oxygen vacancies in the oxide semiconductor layer 144 can be filled; thus, the oxide semiconductor layer which is i-type (intrinsic) or substantially i-type can also be formed.

Note that the second heat treatment is performed in this embodiment after the gate insulating layer 146 is formed; there is no limitation on the timing of the second heat treatment. For example, the second heat treatment may be performed after the gate electrode is formed. Alternatively, the first heat treatment and the second heat treatment may be performed in succession, or the first heat treatment may double as the second heat treatment, or the second heat treatment may double as the first heat treatment.

By performing at least one of the first heat treatment and the second heat treatment as described above, the oxide semiconductor layer 144 can be purified so as to contain impurities other than main components as little as possible.

The gate electrode 148 a and the electrode 148 b can be formed by forming a conductive layer over the gate insulating layer 146 and then by selectively etching the conductive layer. The conductive layer to be the gate electrode 148 a and the electrode 148 b can be formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The details are similar to those of the source electrode 142 a or the like; thus, the description thereof can be referred to.

Next, the insulating layer 150 and the insulating layer 152 are formed over the gate insulating layer 146, the gate electrode 148 a, and the electrode 148 b (see FIG. 9A). The insulating layer 150 and the insulating layer 152 can be formed by a PVD method, a CVD method, or the like. The insulating layer 150 and the insulating layer 152 can be formed using a material including an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, or aluminum oxide.

Note that the insulating layer 150 and the insulating layer 152 are preferably formed using a low dielectric constant material or a low dielectric constant structure (such as a porous structure). This is because when the insulating layer 150 and the insulating layer 152 have a low dielectric constant, capacitance generated between wirings, electrodes, or the like can be reduced and operation at higher speed can be achieved.

Note that although a stacked-layer structure of the insulating layer 150 and the insulating layer 152 is used in this embodiment, an embodiment of the disclosed invention is not limited to this example. A single-layer structure or a stacked-layer structure including three or more layers can also be used. Alternatively, a structure in which the insulating layers are not provided is also possible.

Note that the insulating layer 152 is desirably formed so as to have a flat surface. This is because when the insulating layer 152 has a flat surface, an electrode, a wiring, or the like can be favorably formed over the insulating layer 152 even in the case where the semiconductor device or the like is miniaturized. Note that the insulating layer 152 can be planarized using a method such as chemical mechanical polishing (CMP).

Next, an opening reaching the drain electrode 142 b is formed in the gate insulating layer 146, the insulating layer 150, and the insulating layer 152 (see FIG. 9B). The opening is formed by selective etching with a mask or the like.

After that, the electrode 154 is formed in the opening, and the wiring 156 in contact with the electrode 154 is formed over the insulating layer 152 (see FIG. 9C).

The electrode 154 can be formed in such a manner, for example, that a conductive layer is formed in a region including the opening by a PVD method, a CVD method, or the like and then part of the conductive layer is removed by etching, CMP, or the like.

Specifically, it is possible to employ a method, for example, in which a thin titanium film is formed in a region including the opening by a PVD method and a thin titanium nitride film is formed by a CVD method, and then, a tungsten film is formed so as to be embedded in the opening. Here, the titanium film formed by a PVD method functions to reduce an oxide film (e.g., a natural oxide film) formed on a surface where the titanium film is formed, and to decrease the contact resistance with a lower electrode or the like (here, the drain electrode 142 b). The titanium nitride film formed after the formation of the titanium film has a barrier function for suppressing diffusion of the conductive material. A copper film may be formed by a plating method after the formation of a barrier film of titanium, titanium nitride, or the like.

Note that in the case where the electrode 154 is formed by removing part of the conductive layer, the process is preferably performed so that the surface is planarized. For example, when a thin titanium film or a thin titanium nitride film is formed in a region including the opening and then a tungsten film is formed so as to be embedded in the opening, excess tungsten, titanium, titanium nitride, or the like is removed and the planarity of the surface can be improved by subsequent CMP treatment. The surface including the electrode 154 is planarized in this manner, so that an electrode, a wiring, an insulating layer, a semiconductor layer, or the like can be favorably formed in a later step.

The wiring 156 is formed by forming a conductive layer by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method, and then by patterning the conductive layer. As a material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy including any of these elements as a component, or the like can be used. A material including one of manganese, magnesium, zirconium, beryllium, neodymium, and scandium or a combination of a plurality of these elements may be used. The details are similar to those of the source electrode 142 a and the like.

Through the above steps, the transistor 162 including the oxide semiconductor layer 144 which is purified and the capacitor 164 are completed (see FIG. 9C).

In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is purified and thus contains hydrogen at a concentration of 5×10¹⁹ atoms/cm³ or less, preferably 5×10¹⁸ atoms/cm³ or less, more preferably 5×10¹⁷ atoms/cm³ or less. In addition, the carrier density of the oxide semiconductor layer 144 is, for example, less than 1×10¹²/cm³, preferably less than 1.45×10¹°/cm³, which is sufficiently lower than the carrier density of a general silicon wafer (approximately 1×10¹⁴/cm³). In addition, the off-state current of the transistor 162 is sufficiently small. For example, the off-state current (per unit channel width (1 μm), here) of the transistor 162 at room temperature (25° C.) is 100 zA (1 zA (zeptoampere) is 1×10⁻²¹ A) or less, preferably 10 zA or less.

In this manner, by using the oxide semiconductor layer 144 which is purified and is intrinsic, it becomes easy to sufficiently reduce the off-state current of the transistor. With the use of such a transistor, a semiconductor device in which stored data can be held for an extremely long time can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

Embodiment 3

In this embodiment, the cases where the semiconductor device described in any of the above embodiments is applied to electronic devices will be described with reference to FIGS. 10A to 10F. The cases where the above-described semiconductor device is applied to electronic devices such as a computer, a mobile phone set (also referred to as a mobile phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio reproducing device, and the like), a digital camera, a digital video camera, electronic paper, a television set (also referred to as a television or a television receiver), and the like are described in this embodiment.

FIG. 10A illustrates a notebook personal computer, which includes a housing 701, a housing 702, a display portion 703, a keyboard 704, and the like. The semiconductor device described in any of the above embodiments is provided in at least one of the housings 701 and 702. Thus, a notebook personal computer with sufficiently low power consumption, in which writing and reading of data can be performed at high speed and data can be stored for a long time, can be realized.

FIG. 10B illustrates a portable information terminal (PDA). A main body 711 is provided with a display portion 713, an external interface 715, operation buttons 714, and the like. Further, a stylus 712 for operation of the portable information terminal, or the like is provided. The semiconductor device described in any of the above embodiments is provided in the main body 711. Thus, a portable information terminal with sufficiently low power consumption, in which writing and reading of data can be performed at high speed and data can be stored for a long time, can be realized.

FIG. 10C illustrates an electronic book incorporating electronic paper, which includes two housings, a housing 721 and a housing 723. The housing 721 and the housing 723 include a display portion 725 and a display portion 727, respectively. The housing 721 is connected to the housing 723 by a hinge 737, so that the electronic book can be opened and closed using the hinge 737 as an axis. In addition, the housing 721 is provided with a power switch 731, operation keys 733, a speaker 735, and the like. At least one of the housings 721 and 723 is provided with the semiconductor device described in any of the above embodiments. Thus, an electronic book with sufficiently low power consumption, in which writing and reading of data can be performed at high speed and data can be stored for a long time, can be realized.

FIG. 10D illustrates a mobile phone set, which includes two housings, a housing 740 and a housing 741. Moreover, the housings 740 and 741 in a state where they are developed as illustrated in FIG. 10D can be slid so that one is lapped over the other. Therefore, the size of the mobile phone set can be reduced, which makes the mobile phone set suitable for being carried around. The housing 741 includes a display panel 742, a speaker 743, a microphone 744, operation keys 745, a pointing device 746, a camera lens 747, an external connection terminal 748, and the like. The housing 740 includes a solar cell 749 for charging the mobile phone set, an external memory slot 750, and the like. An antenna is incorporated in the housing 741. The semiconductor device described in any of the above embodiments is provided in at least one of the housings 740 and 741. Thus, a mobile phone set with sufficiently low power consumption, in which writing and reading of data can be performed at high speed and data can be stored for a long time, can be realized.

FIG. 10E illustrates a digital camera, which includes a main body 761, a display portion 767, an eyepiece 763, an operation switch 764, a display portion 765, a battery 766, and the like. The semiconductor device described in any of the above embodiments is provided in the main body 761. Thus, a digital camera with sufficiently low power consumption, in which writing and reading of data can be performed at high speed and data can be stored for a long time, can be realized.

FIG. 10F is a television set, which includes a housing 771, a display portion 773, a stand 775, and the like. The television set 770 can be operated with a switch included in the housing 771 or with a remote controller 780. The semiconductor device described in any of the above embodiments is mounted in the housing 771 and the remote controller 780. Thus, a television set with sufficiently low power consumption, in which writing and reading of data can be performed at high speed and data can be stored for a long time, can be realized.

As described above, the electronic devices described in this embodiment each include the semiconductor device according to any of the above embodiments. Therefore, electronic devices with low power consumption can be realized.

Example 1

In this example, results of measuring the off-state current of a transistor including a purified oxide semiconductor will be described.

First, a transistor with a channel width W of 1 m, which is sufficiently wide, was prepared in consideration of a very small off-state current of a transistor including a purified oxide semiconductor, and the off-state current was measured. FIG. 11 shows the results of measuring the off-state current of the transistor with a channel width W of 1 m. In FIG. 11, the horizontal axis shows a gate voltage VG and the vertical axis shows a drain current ID. In the case where the drain voltage VD is +1 V or +10 V and the gate voltage VG is within the range of −5 V to −20 V, the off-state current of the transistor is found to be smaller than or equal to 1×10⁻¹² A which is the detection limit. In addition, the off-state current (per unit channel width (1 μm), here) of the transistor is found to be smaller than or equal to 1 aA/μm (1×10⁻¹⁸ A/μm).

Next, the results of more accurately measuring the off-state current of the transistor including a purified oxide semiconductor will be described. As described above, the off-state current of the transistor including a purified oxide semiconductor is found to be smaller than or equal to 1×10⁻¹² A which is the detection limit of measurement equipment. Here, the results of measuring more accurate off-state current (a value smaller than or equal to the detection limit of measurement equipment in the above measurement) with the use of an element for characteristic evaluation will be described.

First, the element for characteristic evaluation which is used in a method for measuring current will be described with reference to FIG. 12.

In the element for characteristic evaluation in FIG. 12, three measurement systems 800 are connected in parallel. The measurement systems 800 each include a capacitor 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808. As the transistor 804, the transistor 805, the transistor 806, and the transistor 808, transistors including a purified oxide semiconductor were employed.

In the measurement system 800, one of a source terminal and a drain terminal of the transistor 804, one of terminals of the capacitor 802, and one of a source terminal and a drain terminal of the transistor 805 are connected to a power source (for supplying V2). The other of the source terminal and the drain terminal of the transistor 804, one of a source terminal and a drain terminal of the transistor 808, the other of the terminals of the capacitor 802, and a gate terminal of the transistor 805 are connected to one another. The other of the source terminal and the drain terminal of the transistor 808, one of a source terminal and a drain terminal of the transistor 806, and a gate terminal of the transistor 806 are connected to a power source (for supplying V1). The other of the source terminal and the drain terminal of the transistor 805 and the other of the source terminal and the drain terminal of the transistor 806 are connected to each other and connected to an output terminal.

Note that a potential Vext_b2 for controlling whether to turn on or off the transistor 804 is supplied to the gate terminal of the transistor 804, and a potential Vext_b1 for controlling whether to turn on or off the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vout is output from the output terminal.

Next, a method for measuring current with the use of the element for characteristic evaluation will be described.

First, an initialization period in which a potential difference is generated to measure the off-state current will be briefly described. In the initialization period, the potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808. Accordingly, a potential V1 is supplied to a node A that is connected to the other of the source terminal and the drain terminal of the transistor 804 (that is, the node connected to one of the source terminal and the drain terminal of the transistor 808, the other of the terminals of the capacitor 802, and the gate terminal of the transistor 805). Here, the potential V1 is, for example, a high potential. In addition, the transistor 804 is turned off.

After that, the potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808, so that the transistor 808 is turned off. After the transistor 808 is turned off, the potential V1 is set to a low potential. Still, the transistor 804 is turned off. The potential V2 is equal to the potential V1. Thus, the initialization period is completed. When the initialization period is completed, a potential difference is generated between the node A and one of the source terminal and the drain terminal of the transistor 804. In addition, a potential difference is generated between the node A and the other of the source terminal and the drain terminal of the transistor 808. Accordingly, a small amount of electric charge flows through the transistor 804 and the transistor 808. That is, the off-state current is generated.

Next, a measurement period of the off-state current will be briefly described. In the measurement period, the potential (that is, V2) of one of the source terminal and the drain terminal of the transistor 804 and the potential (that is, V1) of the other of the source terminal and the drain terminal of the transistor 808 are fixed to a low potential. On the other hand, the potential of the node A is not fixed (the node A is in a floating state) in the measurement period. Accordingly, charge flows through the transistor 804, and the amount of charge held at the node A changes over time. The potential of the node A changes depending on the change in the amount of charge held at the node A. That is, the output potential Vout of the output terminal also changes.

FIG. 13 shows details (a timing chart) of the relationship among potentials in the initialization period in which the potential difference is generated and those in the subsequent measurement period.

In the initialization period, first, the potential Vext_b2 is set to a potential (a high potential) at which the transistor 804 is turned on. Thus, the potential of the node A becomes V2, that is, a low potential (VSS). Note that it is not essential to supply a low potential (VSS) to the node A. After that, the potential Vext_b2 is set to a potential (a low potential) at which the transistor 804 is turned off, so that the transistor 804 is turned off. Next, the potential Vext_b1 is set to a potential (a high potential) at which the transistor 808 is turned on. Accordingly, the potential of the node A becomes V1, that is, a high potential (VDD). Then, the potential Vext_b1 is set to a potential at which the transistor 808 is turned off, which places the node A in a floating state and finishes the initialization period.

In the measurement period after the initialization period, the potential V1 and the potential V2 are set such that charge flows to the node A or charge flows out of the node A. Here, the potential V1 and the potential V2 are set to a low potential (VSS). Note that at the time when the output potential Vout is measured, it is necessary to operate an output circuit and thus temporarily set V1 to a high potential (VDD) in some cases. Note that the period in which V1 is set to a high potential (VDD) is made short to such a degree that the measurement is not influenced.

When the potential difference is generated and the measurement period is started as described above, the amount of charge held at the node A changes over time, which causes the potential of the node A to change. This means that the potential of the gate terminal of the transistor 805 changes; thus, the output potential Vout of the output terminal also changes over time.

A method for calculating the off-state current on the basis of the obtained output potential Vout is described below.

The relationship between a potential V_(A) of the node A and the output potential Vout is obtained before calculation of the off-state current. With this relationship, the potential V_(A) of the node A can be obtained using the output potential Vout. In accordance with the above relationship, the potential V_(A) of the node A can be expressed as a function of the output potential Vout by the following equation. V _(A) =F(Vout)  [Formula 1]

Charge Q_(A) of the node A can be expressed by the following equation with the use of the potential V_(A) of the node A, capacitance C_(A) connected to the node A, and a constant (const). Here, the capacitance C_(A) connected to the node A is the sum of the capacitance of the capacitor 802 and other capacitance. Q _(A) =C _(A) V _(A)+const  [Formula 2]

Current I_(A) of the node A is a time derivative of charge which flows to the node A (or charge which flows out of the node A), and is thus expressed by the following equation.

$\begin{matrix} {I_{A} = {\frac{\Delta\; Q_{A}}{\Delta\; t} = \frac{{C_{A} \cdot \Delta}\;{F({Vout})}}{\Delta\; t}}} & \left\lbrack {{Formula}\mspace{14mu} 3} \right\rbrack \end{matrix}$

In this manner, the current I_(A) of the node A can be obtained from the capacitance C_(A) connected to the node A and the output potential Vout of the output terminal.

In accordance with the above method, it is possible to measure leakage current (off-state current) which flows between a source and a drain of a transistor in an off state.

In this example, the transistor 804, the transistor 805, the transistor 806, and the transistor 808 were manufactured using a purified oxide semiconductor with a channel length L of 10 μm and a channel width W of 50 μm. In addition, in the measurement systems 800 which are arranged in parallel, the capacitances of the capacitors 802 were 100 fF, 1 pF, and 3 pF.

Note that VDD was 5 V and VSS was 0 V in the measurement of this example. In the measurement period, Vout was measured while the potential V1 was basically set to VSS and changed to VDD for 100 msec at intervals of 10 sec to 300 sec. In addition, Δt used in calculation of current I which flows through the element was approximately 30000 sec.

FIG. 14 shows the relationship between the elapsed time Time in the above current measurement and the output potential Vout. It can be confirmed from FIG. 14 that the potential changes as time elapses.

FIG. 15 shows the off-state current at room temperature (25° C.) which is calculated in the above current measurement. Note that FIG. 15 shows the relationship between the source-drain voltage V and the off-state current I. It is found from FIG. 15 that the off-state current is about 40 zA/μm under the condition where the source-drain voltage is 4 V. It is also found that the off-state current is smaller than or equal to 10 zA/μm under the condition where the source-drain voltage is 3.1 V. Note that 1 zA represents 10⁻²¹ A.

Furthermore, FIG. 16 shows the off-state current in an environment at a temperature of 85° C., which is calculated in the above current measurement. FIG. 16 shows the relationship between the source-drain voltage V and the off-state current I in an environment at a temperature of 85° C. It is found from FIG. 16 that the off-state current is smaller than or equal to 100 zA/μm under the condition where the source-drain voltage is 3.1 V.

As described above, it is confirmed from this example that the off-state current of a transistor including a purified oxide semiconductor is sufficiently small.

This application is based on Japanese Patent Application serial no. 2010-063929 filed with Japan Patent Office on Mar. 19, 2010, the entire contents of which are hereby incorporated by reference. 

The invention claimed is:
 1. A semiconductor device including a memory cell, the memory cell comprising: a first transistor; a second transistor electrically connected to the first transistor; and a capacitor, wherein the first transistor is a p-channel type transistor and comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region comprising an oxide semiconductor, wherein the first gate electrode, one electrode of the capacitor and one of the second source electrode and the second drain electrode are electrically connected to one another and form a node where an electric charge is held, and wherein the one electrode of the capacitor is the one of the second source electrode and the second drain electrode.
 2. The semiconductor device according to claim 1, wherein the second transistor is an n-channel type transistor.
 3. The semiconductor device according to claim 1, wherein the second transistor is overlapped with at least part of the first transistor.
 4. The semiconductor device according to claim 1, wherein the first channel formation region comprises silicon.
 5. A semiconductor device including a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a memory cell connected between the first wiring and the second wiring, wherein the memory cell comprises: a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region comprising an oxide semiconductor; and a capacitor, wherein the first transistor is a p-channel type transistor, wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to one another and form a node where an electric charge is held, wherein the one electrode of the capacitor is the one of the second source electrode and the second drain electrode, wherein the first wiring and one of the first source electrode and the first drain electrode are electrically connected to each other, wherein the second wiring and the other of the first source electrode and the first drain electrode are electrically connected to each other, wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other, wherein the fourth wiring and the second gate electrode are electrically connected to each other, and wherein the fifth wiring and the other electrode of the capacitor are electrically connected to each other.
 6. The semiconductor device according to claim 5, wherein the second transistor is an n-channel type transistor.
 7. The semiconductor device according to claim 5, wherein the second transistor is overlapped with at least part of the first transistor.
 8. The semiconductor device according to claim 5, wherein the first channel formation region comprises silicon. 